Registers are some small storage areas inside a central processing unit (CPU) that are used to store data, and are used to temporarily store data for an operation and operation results. A register includes a latch or a trigger. Because one latch or trigger can store a 1-bit binary number, N latches or triggers can constitute an N-bit register, where N is a positive integer.
FIG. 1 shows a structural diagram of a circuit of an existing register. As shown in FIG. 1, the register includes a phase-inverted clock generation circuit, an input stage circuit, and two-stage latches (a first-stage latch and a second-stage latch shown in the figure). The phase-inverted clock generation circuit is configured to generate a phase-inverted clock signal. A clock signal and the phase-inverted clock signal are applied together to the input stage circuit, so as to control on and off of the input stage circuit by means of cooperation. The input stage circuit is configured to: import a data signal, and generate a signal for a latch to store. The register includes two working modes: a function mode and a test mode. In the function mode, the register works normally and stores data. In the test mode, a scan in (SI) signal is imported to test overall performance of the register. A specific working principle of the register is as follows: When a scan enable (SE) signal is 0, the register works in the function mode, and a phase-inverted clock signal (denoted as a C1 signal) is generated after a clock signal (denoted as a CP signal) undergoes specific delaying and phase inverting; or when an SE signal is 1, the register works in the test mode, and a CP signal and an SI signal are applied together to generate a C1 signal. The C1 signal, the CP signal, a data signal (denoted as a D signal), and the SE signal are applied together to the input stage circuit. The CP signal and the C1 signal together control the input stage circuit, so that the input stage circuit is turned on only within a short time after a rising edge of the CP signal arrives. The first-stage latch and the second-stage latch work in turn under control of the CP signal. After the rising edge of the CP signal arrives, the second-stage latch is turned off, and the first-stage latch is turned on; and after a falling edge of the CP signal arrives, the first-stage latch is turned off, and the second-stage latch is turned on. When the SE signal is 0 (that is, in the function mode), after the rising edge of the CP signal arrives, whether the input stage circuit is turned on is determined by a level of the D signal, and therefore a phase-inverted signal of the D signal is latched by the first-stage latch; and after the falling edge of the CP signal arrives, a value of the D signal is latched by the second-stage latch. When the SE signal is 1 (that is, in the test mode), after the rising edge of the CP signal arrives, whether the input stage circuit is turned on is unrelated to the D signal and is determined by a level of a C1 signal that is controlled by the SI signal, and therefore a value of the SI signal is latched by the first-stage latch; and after the falling edge of the CP signal arrives, a phase-inverted signal of the SI signal is latched by the second-stage latch.
In the circuit shown in FIG. 1, the phase-inverted clock generation circuit is the key. An existing phase-inverted clock generation circuit is shown in FIG. 2. When an SE signal is 0, a register works in a function mode, and a C1 signal is a signal generated after a CP signal undergoes delaying and phase inverting; or when an SE signal is 1, a register works in a test mode, a C1 signal is controlled by both a CP signal and an SI signal, and the C1 signal is 0 provided that at least one of the CP signal or the SI signal is 1. In this way, after a rising edge of the CP signal arrives, if the SI signal is 1, the C1 signal is 0, and the input stage circuit is turned off; if the SI signal is 0, the C1 signal is a phase-inverted signal obtained after the CP signal undergoes delaying, and the input stage circuit is turned on for a short time within a time period during which both the CP signal and the C1 signal are 1.
In the prior art, delaying and phase inverting of a CP signal are implemented by using two-stage phase inverters plus a NAND gate. Therefore, there are a large quantity of metal oxide semiconductor field effect transistors (MOS transistor for short) used in the existing phase-inverted clock generation circuit, and a circuit topology structure is quite complex, resulting in relatively high power consumption of a circuit.